1. Field of the Invention
This invention relates to a master slice integrated circuit device such as a gate array and more particularly to such a device characterized by the method used for providing power supply circuitry between a main power supply circuit at the periphery of the chip and the internal cell region of the chip.
Master slice type gate arrays can be readily fabricated so as to provide the particular logic circuitry desired by the customer. In this type of gate array, internal cells each comprising one or more transistors of prescribed types are formed in an orderly arrangement on a wafer and external cells (I/O buffers) are formed at a peripheral region of the wafer. The desired logic circuitry is thereafter obtained by selecting the appropriate wiring process or wiring pattern. In gate arrays of this type, the power lines which branch off from the main power circuit region formed on the external cell array region and pass into the internal cell array region are generally formed to be located at predetermined intervals with respect to the regularly arranged internal cells.
As seen in FIG. 5, a conventional gate array comprises a plurality of rows of internal cells C (C.sub.mn . . . C.sub.m+5 n+2) and external cells 20 (20.sub.m . . . 20.sub.m+3) disposed vertically at an internal region of the chip. Each external cell C is constituted of one or more transistors, and internal and external wiring is provided via prescribed contacts (not shown) for interconnecting the internal cells themselves. As a result the vertical pitch P.sub.IN of the internal cells C depends on the type of the internal cells and the number of transistors therein. On the other hand, the pitch P.sub.OUT of the external cells 20 is ordinarily matched to the pitch of pads (not shown) formed exterior of the array. In the case of a master slice, a certain amount of fixed wiring is provided for interconnecting the transistors and the like into fixed devices in advance. Later the final wiring (signal and power lines) is provided for interconnecting the devices formed in advance so as to obtain the particular logic circuitry required by the customer. This final wiring is carried out by making up appropriate wiring patterns (pattern versions), fixing the original and inputting the pattern version to a wiring processing means, such as a computer.
The gate array shown in FIG. 5 has a main power circuit 30 formed on the region of the external cells 20 and power lines l (. . . l.sub.m, l.sub.m+1, l.sub.m+2 . . . ) are provided to branch off from the power circuit region 30 and each supplies power to two rows adjacent of the internal cell array. As will be noted in FIG. 5, the array constituted of the internal cells C and the array constituted of the external cells 20 are out of phase as regards their repetition periods. More specifically, the relationship between the pitch P.sub.OUT of the external cells and the pitch P.sub.IN of the internal cells can be expressed as EQU j P.sub.OUT .noteq.k P.sub.IN ( 1) EQU k&gt;j.gtoreq.1 (2)
where j and k are any positive integers. When the pitch of the positions at which lines l (. . . l.sub.m, l.sub.m+1, l.sub.m+2 . . . ) branch off from the main power circuit region 30 is set to match the pitch P.sub.OUT of the external cells 20 (e.g. when in FIG. 5 these lines are disposed at the boundary positions . . . P.sub.m, P.sub.m+1, P.sub.m+2 . . . ) and the lines are patterned to then extend between adjacent rows of cells C, the periods of repetition of the internal cells C and the external cells 20 in the vertical direction will be out of the phase with one another. Therefore, as can be seen in FIG. 5, each of the power lines l (. . . l.sub.m, l.sub.m+1, l.sub.m+2 . . . ) has a respectively different pattern, or configuration, so that the number of power line pattern versions is equal to the number of power lines.
For ensuring the voltage stability and the like of the power supplied to the individual internal cells, the delivery of power to these cells is effected by a method wherein the power lines shown in FIG. 5 are disposed in an orderly fashion so as each to fall at the boundary region between two adjacent rows of the internal cell array. On the other hand, the branch-off positions of the power lines are disposed at the fixed positions P.sub.m, P.sub.m+1, P.sub.m+2 so that they will fall in a fixed positional relationship to the external cells (20.sub.m . . . 20.sub.m+3) corresponding to contact window positions (X.sub.m+1, Y.sub.m+1), (X.sub.m+2, Y.sub.m+2), (X.sub.m+3, Y.sub.m+3) of the external cells 20.sub.m+1, 20.sub.m+2, 20.sub.m+3 whereby there can be obtained a single and commonly usable branch-off pattern.
FIG. 6 shows the wiring pattern of another gate array having a main power circuit region 30. In this array, signal pads 5 (. . . 5.sub.L, . . . 5.sub.L+5 . . .) are connected with external cells 7 ( . . . 7.sub.L, . . . 7.sub.L+5 . . . ). The external cells 7 are connected with contact windows X (X.sub.a, X.sub.b . . . X.sub.e . . . ) via lead lines a-e (a.sub.L . . . e.sub.L+5). Power lines 9 are formed on the array region of the internal cells 11 so as to be spaced at the pitch P.sub.IN of the internal cells 11 of the array. Main power circuit region 30 is formed on the region of the external cells 7. The pitch of the branch-off positions of the power lines 9 from the main power circuit region is the same as the pitch P.sub.IN of the internal cells. In this case, the spacing intervals of the array of internal cells 11 and the array of external cells are in phase. More specifically, the relationship between the pitch P.sub.OUT of the external cells and the pitch P.sub.IN of the internal cells can be expressed as EQU j P.sub.OUT =k P.sub.IN ( 3)
k&gt;j.gtoreq.1 (2)
where j and k are positive integers.
In this case under consideration, j=4 and k=7 so that the lead lines (a-e) from every fourth external cell 7 have the same pattern. For example, the pattern of the lead lines of external cell 7.sub.L and 7.sub.L+4 have the same pattern. Because of this, only four patten versions are required for fabricating external cells 7.
Nevertheless the wiring method of conventional gate arrays involves the following problems.
(1) In the case where as shown in FIG. 5, the periods of repetition of the external cells 20 and the internal cells C are out of phase, every power line l has a different pattern Moreover, the branch-off portions of the power lines may, depending on their configuration, constitute a hindrance to the provision of the contact windows at the prescribed position, whereby differences may arise between the position of the contact windows between external cells of the same logic type. The result is that differences arise in the patterns of the lead lines from the external cells. As a consequence, there is an increase in the number of power line pattern versions and also, in some cases, in the number of lead line pattern versions. This makes automatic wiring difficult.
(2) In the case where, as shown in FIG. 6 the periods of repetition of the external cells 7 and the internal cells 11 are in phase, the patterns of all power lines 9 are identical and the number of lead line patterns can be limited to the value of j in equation
(3) so that it would appear that the number of pattern versions for the power lines and the lead lines is much smaller than in the case of the out-of-phase arrangement of FIG. 5. However, the contact window patterns are not all the same with respect to the external cells 7. Namely, the number of such patterns is equal to j. Therefore, since the contact windows of the external cells are not all formed in the same fixed position, the actual work of providing the signal lines for connecting the contact windows of the external cells with the contact windows of the internal cells (not shown) is made even more complicated.
On the other hand, arrangement of the external and internal cells in an in-phase relationship diminishes the degree of freedom regarding such basic design factors as the circuitry and size of both types of cells. More specifically, since cell size cannot be freely selected, there is no choice but to fix discrete cell sizes, a necessity which automatically puts a major limitation on the size or the circuitry which can be fitted into each cell.